1. Field of the Invention
The present invention relates to precharge and evaluation circuits for memory sense amplifiers.
2. Related Art
In order to correctly read the data item from a memory cell of a memory matrix, it is customary to compare the current read from the memory matrix cell with the current read from a reference matrix cell or with a reference current, in order to detect the difference between a programmed cell and an erased cell.
For this purpose, memory matrices are usually configured so that reading data from a memory cell is performed by comparing a current that flows across a reference matrix cell (or a reference current) with the current of the selected cell. The difference between the two currents determines the value of the data. If the matrix cell current is higher than reference current then the stored data is a “one” bit; otherwise it is a zero bit.
To get the correct current flowing the selected cells, the drains of the memory transistors associated with a selected column/bitline have to be correctly polarized, as do the gates of the memory transistors associated with a selected row.
A standard approach to bias the drain of a memory cell is to employ cascode circuitry such as is shown in FIGS. 1A and 1B. The YMS signal is connected by the column decoder to the selected bitline coupled to the selected flash cell drain. A load (resistor, p-channel transistor, current source, etc.) is used to sink current to the bitline of the flash cell, passing through the control of the cascode transistor that defines the YMS value.
This circuitry has to guaranty to provide the correct flash cell drain value (about 1V) as soon as possible and to prevent the flash cell drain from being over this value in order to prevent a soft writing problem.
The value of the voltage at the gate of the cascode transistor limits maximum value of YMS (that is at its source) and so limits the maximum value of the voltage on the selected bitline that is connected to it through the column decoder. The voltage at the gate of the cascode transistor can be obtained as a fixed voltage as shown in FIG. 1A, for example using a voltage reference, or by using feedback circuitry having the YMS signal (that is similar to Bitline value) as an input as shown in FIG. 1B. This kind of circuitry is usually used to precharge both the selected matrix cell drain and the reference cell drain. Fast polarization of flash cells allows fast access time and improves performance.
An illustrative conventional standard sense amplifier is shown in FIG. 2. The diode-connected p-channel transistors are used as loads to charge the matrix and reference bit lines. These devices may also be used to compare the flash cell current and the reference cell current by mirroring these currents in a mirror comparator. The drain nodes of the p-channel transistors are sometimes referred to as evaluation nodes (labeled “MAT” and “REF” to designate the matrix and reference evaluation nodes, respectively).
Flash memory cells usually sink a very low current, but their drains are almost always coupled to a very long bitline having a high inherent capacitance that has to be charged to the target value quickly to meet the memory access time specification. To solve this problem, large transistors are often used because they are able to sink the current necessary to precharge this large capacitance. This presents another drawback due to their dimensions and their terminal capacitance, making the evaluation nodes very slow during evaluation mode where the currents are very low.
An illustrative conventional current mirror sense amplifier (a very basic scheme) having a cascode device with feedback circuitry as shown in FIG. 2 will be described. FIG. 2 illustrates a very basic current mirror sense amplifier having a local reference but persons skilled in the art will appreciate that the same issues will arise when a global reference that can be obtained in any different way, for example a current generator, is employed.
The leftmost p-channel transistor is used to furnish current to the bitline of the flash cell, passing through the control of its associated cascode transistor. The rightmost p-channel transistor is used to furnish current to the bitline of the reference cell, passing through the control of the reference cascode transistor.
In the current mirror sense amplifier shown in FIG. 2, the two p-channel transistors are shown in diode configuration, but could also be in other configurations such as mirror configuration. The two Cascode transistors have their gates controlled by feedback circuitry with input values YMS_M and YMS_R, respectively. YMS_M is connected by the column decoder to the selected matrix cell bitline/drain and YMS_R is connected by a dummy column decoder to the reference bitline/drain.
The most simple feedback circuitry may be an inverter but is usually more complex. When the selected matrix flash and reference cell are correctly polarized to their static values, in gate and drain, they sink respectively a current Imat in the matrix cell and a current Iref in the reference cell, and diode-connected p-channel matrix transistor current I_M is equal to Imat while the diode-connected p-channel reference transistor current I_R is equal to Iref. Before settling to static values, diode-connected p-channel matrix and reference transistors must also furnish the transient currents needed to charge the bitlines to the correct values.
Before getting static values I_M=Imat+Icmat and I_R=Iref+Icref, where Icmat and Icref represent the total transient capacitance component related respectively to the reference column path and to the matrix column path. The capacitance of the bitlines is very large and so the current Icmat needed to precharge it is very high, while flash current Imat is very low. Only the issue of precharging the bitlines will be considered in this analysis. Static values are obtained when Icmat≈0 and Icref≈0.
There are usually two basic phases in this kind of sensing operation. The first is a precharge phase, during which the flash cell terminals are polarized to the target value. The next phase is the evaluation phase where the flash cell status (zero or one bit for single level) is detected by comparing the currents I_M (that should be ≈Imat in this phase) and I_R (that should be ≈Iref in this phase). If Imat is less than Iref, the flash cell has to be evaluated as containing a “0” bit. If Imat is more than Iref, the flash cell has to be evaluated as containing a “1” bit.
The sensing operation performs a comparison between I_M=Imat+Icmat and I_R=Iref+Icref. Therefore, the sense operation performs correctly if done during the evaluation phase when Imat<IrefI_M is less than I_R and if done during the evaluation phase when Imat>IrefI_M is greater than I_R. If transient (i.e., capacitive) currents are not negligible during the evaluation phase these current relationships may not be true and the sense operation could fail. In particular in the case in which Icmat>Icref and is compared to Iref, the result could be I_M=Imat+Icmat>I_R=Iref+Icref, even if Imat=0, thus erroneously detecting a “0” bit as “1” bit.
This is particularly critical in the case in which large diode-connected and cascode transistors are used, because when the selected cell contains a “0” bit, to sense the correct information the current I_M that flows through these transistors has to become close to zero during the evaluation phase, but due to the large transistor dimensions they take a long time to reach their turn-off point. This time often is not acceptable when a fast access time is required.
It is very important to start the evaluation phase when Icmat and Icref are negligible especially in the case in which Icmat is different from Icref, so that the precharge phase has to be very fast to achieve a fast access time. To do this a very high current has to be furnished to the high capacitance bitlines by the sense circuitry.
The bitline/drain of the selected matrix flash cell is biased through the current flowing through the matrix diode-connected transistor and it is biased by the control of the matrix cascode transistor to a value that usually is in the range of about of 1V. The same happens for reference side through the reference diode-connected transistor and the reference cascode transistor. After this precharge phase, the p-channel matrix diode-connected transistor should sink the same current Imat of the selected flash cell and the reference diode-connected transistor should sink the same current Iref of the flash reference cell. Because both p-channel transistors are connected in diode configuration they operate in their saturation region. Therefore, as first approximation their current follows the following relationship:Id=K*W/L*(VGS−VTHp)2.  (1)where W is the width, L is the length and K is a typical process parameter of the transistor. VGS is the voltage between the source and the gate. VTHp is the p-channel threshold voltage. In this case the matrix and reference transistors are considered to be identical but of course they could be different.
The source voltage for both transistors is the supply voltage VDD. The gate of the p-channel matrix diode-connected transistor is at a voltage VMAT, while the gate of the p-channel reference diode-connected transistor is at a voltage VREF. These connections are the evaluation nodes (MAT and REF) of the circuit. To detect the cell information a comparator is used having its inputs connected to the evaluation nodes at the gate/drain connections of the p-channel matrix diode-connected transistor and the p-channel reference diode-connected transistor.
A sensing circuit using an illustrative comparator is shown in FIG. 3. In this case transistor P1 is coupled to mirror the current of the matrix diode-connected transistor and transistor P2 is coupled to mirror the current of the reference diode-connected transistor. For simplicity assume that P1 and P2 have the same dimensions as the diode-connected transistors. Accordingly, P1 sinks statically a current equal to Imat, and P2 sinks statically a current equal to Iref.
The diode-connected p-channel transistors have to furnish very high current to quickly precharge the large capacitance associated with long bitlines, and working in mirror configuration they need to have a long length L to minimize any possible mirroring error. For these reasons they are very large and have high gate capacitance. Consequently p-channel transistors P1 and P2 are also very large. The large W and L cause their gate capacitance to be very high, with the result that the evaluation nodes that are respectively connected to the gates of the p-channel diode connected transistors and transistors P1 and P2, present a load having a large capacitance. This slows the sense process, because the currents Imat, and Iref are very low and take a significant amount of time to move the voltages at these high-capacitance evaluation nodes.
Finally, the increasing of the voltages at the evaluation nodes to reach their target values dramatically reduces the current that the diode-connected transistors are able to sink. According relationship (1):I—M=K*Wm/Lm*((VDD−VMAT−VTHp)2I—R=K*Wr/Lr*((VDD−VREF−VTHp)2 where Wm, Lm are the width and length of the p-channel matrix diode-connected transistor and Wr and Lr are the width and length of the p-channel reference diode-connected transistor.
The higher the voltages VMAT and VREF, the lower the currents through the p-channel matrix and reference diode-connected transistors that are needed to charge the bitlines. This is particularly critical especially during the last part of the precharge phase, that for this reason can take a long time. Moreover, the matrix and reference cascode transistors need to be very large because they also have to be able, for the same reasons, to furnish a very high current to quickly complete the precharge phase.
Several solutions have been used to solve this problem. One such solution is illustrated in FIG. 4 in which a parallel precharge path is added to the sense amplifier. This parallel path includes one p-channel precharge transistor connected to the matrix evaluation node (MAT) and another p-channel precharge transistor is connected to the reference evaluation node (REF). Their gates are coupled to ground during the precharge phase to turn them on during the precharge phase. In this way the precharge current is augmented during the precharge phase since these additional transistors can sink high current during the precharge phase.
The precharge transistors are on for a period defined by the additional control signal Prech that is tied to ground during this period and that is tied to VDD during the evaluation phase to turn off the precharge transistors. In this way it is possible to furnish all the current needed to quickly bias the bitlines without the issue of significant current reduction due to the voltage rise at the evaluation nodes.
The solution shown in FIG. 4 speeds up the precharge phase but has the drawback that there is a significant risk that the evaluation nodes are biased at values that are too high with respect the target values at the end of the precharge phase. It is very difficult to find the correct duration of this new phase to avoid this problem. Since only low currents flow during the evaluation phase, the evaluation nodes still need to be discharged to the correct values after the precharge phase, a finite time is needed and a sensing error can thus occur.
Other parallel precharge solutions using transistors having different thresholds have been proposed to avoid this risk, but such solutions are not efficient enough to allow significant reduction of the sizes of the p-channel diode-connected transistors and to reduce access time.